In pursuit of higher performances and lower computational power consumption, the critical dimensions (cd’s) of logic transistor channels have shrunk to a handful of nanometers. At these cd's, quantum effects reduce the performance gains which can be achieved with further scaling. In addition, today's devices are made by lithographically patterning device channel cd. As patterned cd is reduced, cd variation increases. Device specifications must accommodate variation and as a result, cd patterning is an additional extrinsic barrier to scaling. Finally, the high temperatures used to grow bulk semiconductors prevent logic devices from scaling vertically. Despite these challenges, demand for performance and efficiency improvements persist and are driven by the explosive growth in computationally heavy markets such as cloud computing, artificial intelligence (AI), edge computing, IOT, and data analytics.
SixLine addresses these barriers through the direct integration of semiconducting carbon nanotubes with conventional fab materials and production environments, using proven, room temperature deposition processes.
At nanometer scale channel cd’s, the charge carrier mobilities of carbon nanotubes are among the highest of any known material and outperform silicon, germanium, bulk semiconductors, and 2D materials. Semiconducting carbon nanotube devices will yield significantly higher performance and lower power draw than state-of-the-art materials.
In addition, the channel cd of a carbon nanotube (its diameter) is defined during synthesis, not through patterning. SixLine methods enable control over the diameter of semiconductor carbon nanotubes and will remove channel cd as a significant source of device variability.
Finally, SixLine is commercializing methods to deposit semiconducting carbon nanotubes onto arbitrary substrates with high throughput and -critically - at room temperature. These techniques integrate seamlessly with silicon and will enable fabrication of logic devices with an arbitrary number of high performance transistor layers, breaking historical constraints on Moore's law scaling.